MC68HC05C9A Datasheet, PDF (67/124 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
characters. In cases where there is only one SPI slave MCU, its SS line could be tied to V_SS as long as
CPHA = 1 clock modes are used.
10.4 Functional Description
Figure 10-2 shows a block diagram of the serial peripheral interface circuitry. When a master device
transmits data to a slave via the MOSI line, the slave device responds by sending data to the master
device via the master’s MISO line. This implies full duplex transmission with both data out and data in
synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and
eliminates the need for separate transmit-empty and receive-full status bits. A single status bit (SPIF) is
used to signify that the input/output (I/O) operation has been completed.
The SPI is double buffered on read, but not on write. If a write is performed during data transfer, the
transfer occurs uninterrupted, and the write will be unsuccessful. This condition will cause the write
collision (WCOL) status bit in the SPSR to be set. After a data byte is shifted, the SPIF flag of the SPSR
is set.
In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR,
until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of
data and then SCK goes idle again.
SPI SHIFT REGISTER
76543210
S
M
PD2/
MISO
M
PD3/
S MOSI
INTERNAL DATA BUS
SPDR ($000C)
INTERNAL
CLOCK
(XTAL ÷2)
SPIE
SPE
MSTR
SPIF
WCOL
MODF
DIVIDER
÷ 2 ÷ 4 ÷ 16 ÷ 32
SPI
CONTROL
SPI INTERRUPT REQUEST
SELECT
SPI CLOCK (MASTER)
SPR1 SPR0
CLOCK
LOGIC
MSTR CPHA CPOL
SPI
CLOCK
SLAVE
SPI
CLOCK
MASTER
PD5/
SS
PD4/
SCK
7
SPI CONTROL REGISTER (SPCR) SPIE
SPI STATUS REGISTER (SPSR) SPIF
SPI DATA REGISTER (SPDR) BIT 7
6
SPE
WCOL
BIT 6
5
DWOM
0
BIT 5
4
MSTR
MODF
BIT 4
3
CPOL
0
BIT 3
2
CPHA
0
BIT 2
1
SPR1
0
BIT 1
0
SPR2
0
BIT 0
$000A
$000B
$000C
Figure 10-2. Serial Peripheral Interface Block Diagram
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
Freescale Semiconductor
67