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MC68HC05C9A Datasheet, PDF (115/124 Pages) Freescale Semiconductor, Inc – Microcontrollers
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B.4.3 4.5–5.5-Volt High-Speed Control Timing
Num
Operating frequency
Master
Slave
Characteristic(1)
Cycle time
1
Master
Slave
Enable lead time
2
Master
Slave
Enable lag time
3
Master
Slave
Clock (SCK) high time
4
Master
Slave
Clock (SCK) low time
5
Master
Slave
Data setup time (inputs)
6
Master
Slave
Data hold time (inputs)
7
Master
Slave
8
Slave access time (time to data active from
high-impedance state)
9 Slave disable time (hold time to high-impedance state)
Data valid
10
Master (before capture edge)
Slave (after enable edge)(3)
Data hold time (outputs)
11
Master (after capture edge)
Slave (after enable edge)
Rise time (20% VDD to 70% VDD, CL = 200 pF)
12
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
Fall time (70% VDD to 20% VDD, CL = 200 pF)
13
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
1. VDD = 4.5–5.5 Vdc
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
Control Timing
Symbol
Min
Max
Unit
fOP(M)
fOP(S)
tcyc(M)
tcyc(S)
tLead(M)
tLead(S)
tLag(M)
tLag(S)
tW(SCKH)M
tW(SCKH)S
tW(SCKL)M
tW(SCKL)S
tSU(M)
tSU(S)
tH(M)
tH(S)
tA
tDIS
tV(M)
tV(S)
tHO(M)
tHO(S)
tRM
tRS
tFM
tFS
dc
0.5
dc
4.1
2.0
—
244
—
Note(2)
—
122
—
Note(2)
—
366
—
166
—
93
—
166
—
93
—
49
—
49
—
49
—
49
—
0
61
—
122
0.25
—
—
122
0.25
—
0
—
—
50
—
1.0
—
50
—
1.0
fOP
MHz
tcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
tcyc(M)
ns
tcyc(M)
ns
ns
µs
ns
µs
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
Freescale Semiconductor
115
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