MC68HC05C9A Datasheet, PDF (68/124 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface (SPI)
In a slave mode, the slave select start logic receives a logic low at the SS pin and a clock at the SCK pin.
Thus, the slave is synchronized with the master. Data from the master is received serially at the MOSI
line and loads the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred
to the read buffer. During a write cycle, data is written into the shift register, then the slave waits for a clock
train from the master to shift the data out on the slave’s MISO line.
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave interconnections.
PD3/MOSI
SPI SHIFT REGISTER
76543210
SPDR ($000C)
PD2/MISO
PD5/SS
I/O PORT
PD4/SCK
SPI SHIFT REGISTER
76543210
SPDR ($000C)
MASTER MCU
SLAVE MCU
Figure 10-3. Serial Peripheral Interface
Master-Slave Interconnection
10.5 SPI Registers
This subsection describes the three registers in the SPI which provide control, status, and data storage
functions. These registers are:
• Serial peripheral control register (SPCR)
• Serial peripheral status register (SPSR)
• Serial peripheral data I/O register (SPDR)
10.5.1 Serial Peripheral Control Register
The SPI control register (SPCR), shown in Figure 10-4, controls these functions:
• Enables SPI interrupts
• Enables the SPI system
• Selects between standard CMOS or open drain outputs for port D
• Selects between master mode and slave mode
• Controls the clock/data relationship between master and slave
• Determines the idle level of the clock pin
Address:
Read:
Write:
Reset:
$000A
Bit 7
6
5
4
3
2
SPIE
SPE
DWOM MSTR
CPOL
CPHA
0
0
0
0
0
1
U = Undetermined
Figure 10-4. SPI Control Register (SPCR)
1
SPR1
U
Bit 0
SPR0
U
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
68
Freescale Semiconductor