MC68HC05C9A Datasheet, PDF (97/124 Pages) Freescale Semiconductor, Inc – Microcontrollers

5.0-Volt Serial Peripheral Interface Timing
12.9 5.0-Volt Serial Peripheral Interface Timing
No.
Characteristic⁽¹⁾
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
f_OP(M)
f_OP(S)
dc
0.5
f_OP
dc
2.1
MHz
Cycle time
1
Master
Slave
t_CYC(M)
2.0
—
t_CYC
t_CYC(S)
480
—
ns
Enable lead time
2
Master
Slave
t_Lead(M)
Note⁽²⁾
—
ns
t_Lead(S)
240
—
Enable lag time
3
Master
Slave
t_Lag(M)
Note⁽²⁾
—
ns
t_Lag(S)
720
—
Clock (SCK) high time
4
Master
Slave
t_W(SCKH)M
340
t_W(SCKH)S
190
—
ns
—
Clock (SCK) low time
5
Master
Slave
t_W(SCKL)M
340
t_W(SCKL)S
190
—
ns
—
Data setup time (inputs)
6
Master
Slave
t_SU(M)
t_SU(S)
100
—
ns
100
—
Data hold time (inputs)
7
Master
Slave
8
Slave access time (time to data active from
high-impedance state)
t_H(M)
t_H(S)
t_A
100
—
ns
100
—
0
120
ns
9 Slave disable time (hold time to high-impedance state)
Data Valid
10
Master (before capture edge)
Slave (after enable edge)⁽³⁾
t_DIS
t_V(M)
t_V(S)
—
0.25
—
240
ns
—
t_CYC(M)
240
ns
Data hold time (outputs)
11
Master (after capture edge)
Slave (after enable edge)
t_HO(M)
t_HO(S)
0.25
0
—
t_CYC(M)
—
ns
Rise time (20% V_DD to 70% V_DD, C_L = 200 pF)
12
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t_RM
—
100
ns
t_RS
—
2.0
µs
Fall time (70% V_DD to 20% V_DD, C_L = 200 pF)
13
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t_FM
—
100
ns
t_FS
—
2.0
µs
1. V_DD = 5.0 Vdc ± 10%; V_SS = 0 Vdc, T_A = –40 to +125°C, unless otherwise noted. Refer to Figure 12-9 and Figure 12-10
for timing diagrams.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
Freescale Semiconductor
97