MC68HC05C9A Datasheet, PDF (36/124 Pages) Freescale Semiconductor, Inc – Microcontrollers

Resets
Address: $001E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
COPF
CME
COPE
CM1
CM0
Write:
Reset: 0
0
0
U
0
0
0
0
= Unimplemented
U = Undetermined
Figure 5-5. COP Control Register (COPCR)
COPF — Computer Operating Properly Flag
Reading the COP control register clears COPF.
1 = COP or clock monitor reset has occurred.
0 = No COP or clock monitor reset has occurred.
CME — Clock Monitor Enable Bit
This bit is readable any time, but may be written only once.
1 = Clock monitor enabled
0 = Clock monitor disabled
COPE — COP Enable Bit
This bit is readable any time. COPE, CM1, and CM0 together may be written with a single write, only
once, after reset. This bit is cleared by reset.
1 = COP enabled
0 = COP disabled
CM1 — COP Mode Bit 1
Used in conjunction with CM0 to establish the COP timeout period, this bit is readable any time. COPE,
CM1, and CM0 together may be written with a single write, only once, after reset. This bit is cleared by
reset. See Table 5-1 for timeout period options.
CM0 — COP Mode Bit 0
Used in conjunction with CM1 to establish the COP timeout period, this bit is readable any time. COPE,
CM1, and CM0 together may be written with a single write, only once, after reset. This bit is cleared by
reset. See Table 5-1 for timeout period options.
Bits 7–5 — Not Used
These bits always read as 0.
Table 5-1. COP Timeout Period
CM1
0
0
1
1
CM0
0
1
0
1
f_OP/2¹⁵ Divide By
1
4
16
64
Timeout Period
(f_OSC = 2.0 MHz)
32.77 ms
131.07 ms
524.29 ms
2.097 s
Timeout Period
(f_OSC = 4.0 MHz)
16.38 ms
65.54 ms
262.14 ms
1.048 s
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
36
Freescale Semiconductor