MC68HC05C9A Datasheet, PDF (34/124 Pages) Freescale Semiconductor, Inc – Microcontrollers

Resets
5.3 RESET Pin
The MCU is reset when a logic 0 is applied to the RESET input for a period of one and one-half machine
cycles (t_RL). However, to differentiate between an external reset and an internal reset (generated from the
COP or clock monitor), any externally driven reset must be active (logic 0) for at least eight t_cyc.
VDD
tVDDR
OSC1(2)
INTERNAL
CLOCK(1)
INTERNAL
ADDRESS
BUS(1)
INTERNAL
DATA
BUS(1)
4064
tCYC
tCYC
$3FFE $3FFF
NEW
PC
NEW
PC
NEW
PCH
NEW
PCL
DUMMY
OP
CODE
RESET NOTE 4
$3FFE $3FFE $3FFE $3FFE $3FFF
NEW
PC
NEW
PC
tRL
NOTE 3
PCH
PCL
DUMMY
OP
CODE
Notes:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is meant to represent only time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
4. RESET outputs V_OL during 4064 power-on reset cycles.
Figure 5-2. Power-On Reset and RESET
5.4 Computer Operating Properly (COP) Reset
This device includes a watchdog COP feature which guards against program run-away failures. A timeout
of the COP timer generates a COP reset. The COP watchdog is a software error detection system that
automatically times out and resets the MCU if not cleared periodically by a program sequence.
The COP is controlled with two registers, one to reset the COP timer and the other to enable and control
COP and clock monitor functions.
Figure 5-3 shows a block diagram of the COP.
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
34
Freescale Semiconductor