MC9S08SG8 Datasheet, PDF (79/310 Pages) Freescale Semiconductor, Inc – Microcontrollers

6.6.1.3 Port A Pull Enable Register (PTAPE)
Chapter 6 Parallel Input/Output Control
7
R
0
W
Reset:
0
6
5
4
3
2
1
0
R
R
PTAPE3
PTAPE2
PTAPE1
0
0
0
0
0
0
Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)
Table 6-4. PTAPE Register Field Descriptions
0
PTAPE0
0
Field
Description
5:4
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Reserved
3:0
PTAPE[3:0]
Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or pull-down
device is enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port A bit n.
1 Internal pull-up/pull-down device enabled for port A bit n.
6.6.1.4 Port A Slew Rate Enable Register (PTASE)
7
R
0
W
Reset:
0
6
5
4
3
2
1
0
R
R
PTASE3
PTASE2
PTASE1
0
1
1
1
1
1
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
Table 6-5. PTASE Register Field Descriptions
0
PTASE0
1
Field
Description
5:4
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Reserved
3:0
PTASE[3:0]
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
MC9S08SG8 MCU Series Data Sheet, Rev. 0
Freescale Semiconductor
PRELIMINARY
79