MC9S08SG8 Datasheet, PDF (69/310 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 Resets, Interrupts, and General System Control
5.7.4 System Options Register 2 (SOPT2)
This high page register contains bits to configure MCU specific features on the MC9S08SG8 devices.
7
6
5
4
3
2
R
0
0
0
COPCLKS¹ COPW¹
ACIC
W
Reset:
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-5. System Options Register 2 (SOPT2)
1 _{This bit can be written only one time after reset. Additional writes are ignored.}
Table 5-6. SOPT2 Register Field Descriptions
1
0
T1CH1PS T1CH0PS
0
0
Field
Description
7
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
COPCLKS 0 Internal 1-kHz clock is source to COP.
1 Bus clock is source to COP.
6
COPW
COP Window — This write-once bit selects the COP operation mode. When set, the 0x55-0xAA write sequence
to the SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the
first 75% of the selected period will reset the MCU.
0 Normal COP operation
1 Window COP operation (only if COPCLKS = 1)
4
ACIC
Analog Comparator to Input Capture Enable— This bit connects the output of ACMP to TPM1 input channel 0.
0 ACMP output not connected to TPM1 input channel 0.
1 ACMP output connected to TPM1 input channel 0.
1
TPM1CH1 Pin Select— This bit selects the location of the TPM1CH1 pin of the TPM1 module.
T1CH1PS 0 TPM1CH1 on PTB5.
1 TPM1CH1 on PTC1.
0
TPM1CH0 Pin Select— This bit selects the location of the TPM1CH0 pin of the TPM1 module.
T1CH0PS 0 TPM1CH0 on PTA0.
1 TPM1CH0 on PTC0.
MC9S08SG8 MCU Series Data Sheet, Rev. 0
Freescale Semiconductor
PRELIMINARY
69