MC9S08SG8 Datasheet, PDF (277/310 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
A.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-4. ESD and Latch-up Test Conditions
Model
Human
Body
Machine
Description
Series resistance
Storage capacitance
Number of pulses per pin
Series resistance
Symbol
R1
C
—
R1
Value
1500
100
3
0
Unit
Ω
pF
Ω
Storage capacitance
C
Number of pulses per pin
—
Latch-up Minimum input voltage limit
Maximum input voltage limit
200
pF
3
– 2.5
V
7.5
V
Table A-5. ESD and Latch-Up Protection Characteristics
No.
Rating¹
Symbol
Min
Max Unit
1
Human body model (HBM)
V_HBM
± 2000
—
V
2
Charge Device Model (CDM)
V_CDM, corner pins
V_CDM, all other pins
+/- 750
+/- 500
–
V
3
Latch-up Current at T_A = 125°C
I_LAT
+/- 100
–
mA
1 _{Parameter is achieved by design characterization on a small sample size from typical devices under typical}
conditions unless otherwise noted.
MC9S08SG8 MCU Series Data Sheet, Rev. 0
Freescale Semiconductor
PRELIMINARY
277