MC9S08SG8 Datasheet, PDF (68/310 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 Resets, Interrupts, and General System Control
5.7.3 System Options Register 1 (SOPT1)
This high page register is a write-once register so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. SOPT1 should be written during the user’s reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
7
6
5
4
3
2
1
0
R
COPT
W
0
0
0
0
STOPE
IICPS
Reset:
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-4. System Options Register 1 (SOPT1)
Table 5-5. SOPT1 Register Field Descriptions
Field
Description
7:6
COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
COPT[1:0] COPCLKS in SOPT2 defines the COP timeout period. See Table 5-1.
5
STOPE
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
2
IICPS
IIC Pin Select — This bit selects the location of the SDA and SCL pins of the IIC module.
0 SDA on PTA2, SCL on PTA3.
1 SDA on PTB6, SCL on PTB7.
MC9S08SG8 MCU Series Data Sheet, Rev. 0
68
PRELIMINARY
Freescale Semiconductor