MC9S08SG8 Datasheet, PDF (290/310 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
A.12 AC Characteristics
This section describes timing characteristics for each peripheral system.
A.12.1 Control Timing
Table A-12. Control Timing
Num C
Rating
Symbol
Min
Typ¹
Max Unit
1
P Bus frequency (t_cyc = 1/f_Bus)
f_Bus
dc
—
20
MHz
2 P Internal low power oscillator period
t_LPO
700
1300 µs
3
P _{External reset pulse width}²
t_extrst
1.5 x t_cyc
—
ns
4
P _{Reset low drive}³
t_rstdrv
34 x t_cyc
—
ns
5
P
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
t_MSSU
25
—
ns
6
P
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes ⁴
t_MSH
25
—
µs
8
Pin interrupt pulse width
P Asynchronous path²
Synchronous path⁵
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)⁵
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
9
D
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t_ILIH, t_IHIL
100
—
1.5 x t_cyc
t_Rise, t_Fall
—
40
—
75
t_Rise, t_Fall
—
11
—
35
—
ns
—
ns
—
—
ns
—
1 _{Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.}
2 _{This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to}
override reset requests from internal sources.
3 _{When any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of tcyc.}
4 _{To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD}
rises above V_LVD.
5 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.}
RESET PIN
t_extrst
Figure A-10. Reset Timing
MC9S08SG8 MCU Series Data Sheet, Rev. 0
290
PRELIMINARY
Freescale Semiconductor