MC9S08SG8 Datasheet, PDF (155/310 Pages) Freescale Semiconductor, Inc – Microcontrollers

Internal Clock Source (S08ICSV2)
If EREFSTEN is set and the ERCLKEN bit is written to 1, the external reference clock will keep running
during stop mode in order to provide a fast recovery upon exiting stop.
10.4.7 Fixed Frequency Clock
The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source for
peripheral modules. The ICS provides an output signal (ICSFFE) which indicates when the ICS is
providing ICSOUT frequencies four times or greater than the divided FLL reference clock (ICSFFCLK).
In FLL Engaged mode (FEI and FEE) this is always true and ICSFFE is always high. In ICS Bypass
modes, ICSFFE will get asserted for the following combinations of BDIV and RDIV values:
• BDIV=00 (divide by 1), RDIV ≥ 010
• BDIV=01 (divide by 2), RDIV ≥ 011
• BDIV=10 (divide by 4), RDIV ≥ 100
• BDIV=11 (divide by 8), RDIV ≥ 101
MC9S08SG8 MCU Series Data Sheet, Rev. 0
Freescale Semiconductor
PRELIMINARY
155