MC9S08SG8 Datasheet, PDF (293/310 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
A.12.3 SPI
Table A-14 and Figure A-14 through Figure A-17 describe the timing requirements for the SPI system.
Table A-14. SPI Electrical Characteristic
Num¹ C
Rating²
Symbol
Min
Max
Unit
1
P Cycle time
Master t_SCK
2
Slave _tSCK
4
2048
t_cyc
—
t_cyc
2
P Enable lead time
Master _tLead
—
Slave _tLead
1/2
1/2
t_SCK
—
t_SCK
3
P Enable lag time
Master _tLag
—
Slave _tLag
1/2
1/2
t_SCK
—
t_SCK
4
P Clock (SPSCK) high time
Master and Slave
t_SCKH 1/2 t_SCK – 25
—
ns
5
P Clock (SPSCK) low time Master
and Slave
t_SCKL ^{1/2 t}SCK ^{– 25}
—
ns
6
P Data setup time (inputs)
Master _tSI(M)
30
Slave _tSI(S)
30
—
ns
—
ns
7
P Data hold time (inputs)
Master _tHI(M)
30
Slave _tHI(S)
30
8
P Access time, slave³
t_A
0
9
P Disable time, slave⁴
t_dis
—
—
ns
—
ns
40
ns
40
ns
10
P Data setup time (outputs)
Master _tSO
25
Slave _tSO
25
—
ns
—
ns
11
P Data hold time (outputs)
Master _tHO
–10
Slave _tHO
–10
—
ns
—
ns
12
P Operating frequency
Master _fop
f_Bus/2048
f_Bus/2
Hz
Slave _fop
dc
f_Bus/4
1 _{Refer to Figure A-14 through Figure A-17.}
2 _{All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI}
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
3 _{Time to data active from high-impedance state.}
4 _{Hold time to high-impedance state.}
MC9S08SG8 MCU Series Data Sheet, Rev. 0
Freescale Semiconductor
PRELIMINARY
293