MC9S08SG8 Datasheet, PDF (67/310 Pages) Freescale Semiconductor, Inc – Microcontrollers

Field
3
ILAD
1
LVD
Chapter 5 Resets, Interrupts, and General System Control
Table 5-3. SRS Register Field Descriptions
Description
Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented
memory address.
0 Reset not caused by an illegal address
1 Reset caused by an illegal address
Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will
occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
5.7.2 System Background Debug Force Reset Register (SBDFR)
This high page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
BDFR¹
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{BDFR is writable only through serial background debug commands, not from user programs.}
Figure 5-3. System Background Debug Force Reset Register (SBDFR)
Table 5-4. SBDFR Register Field Descriptions
Field
0
BDFR
Description
Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.
MC9S08SG8 MCU Series Data Sheet, Rev. 0
Freescale Semiconductor
PRELIMINARY
67