MC9S08SG8 Datasheet, PDF (29/310 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Pins and Connections
Table 2-1. . Pin Availability by Package Pin-Count
Pin Number
Lowest
Priority
Highest
20-pin 16-pin 8-pin Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
Alt5
1
1
1
RESET¹
2
2
2
BKGD
MS
3
3
4
4
5
5
6
6
7
7
8
8
9
—
10
—
11
—
12
—
13
9
14
10
3
4
— PTB7
— PTB6
— PTB5
— PTB4
— PTC3
— PTC2
— PTC1
— PTC0
— PTB3
— PTB2
V_DD
V_SS
SCL²
EXTAL
SDA²
XTAL
TPM1CH1³ SS
PTC0⁴
TPM2CH1 MISO
PTC0⁴
PTC0⁴
ADP11
PTC0⁴
ADP10
TPM1CH1³ PTC0⁴
ADP9
TPM1CH0³ PTC0⁴
ADP8
PIB3
MOSI
PTC0⁴
ADP7
PIB2
SPSCK
PTC0⁴
ADP6
15
11
— PTB1
PIB1
TxD
ADP5
16
12
— PTB0
PIB0
RxD
ADP4
17
13
5 PTA3
PIA3
SCL²
ADP3
18
14
6 PTA2
PIA2
SDA²
ADP2
ACMPO
19
15
7 PTA1
PIA1
TPM2CH0
ADP1⁵
ACMP–⁵
20
16
8 PTA0
PIA0
TPM1CH0³ TCLK
ADP0⁵
ACMP+⁵
1 _{Pin is open drain with an internal pullup that is always enabled. Pin does not contain a clamp diode to VDD}
and should not be driven above V_DD. The voltage measured on the internally pulled up RESET will not be
pulled to V_DD. The internal gates connected to this pin are pulled to V_DD.
2 _{IIC pins can be repositioned using IICPS in SOPT2, default reset locations are on PTA2 and PTA3.}
3 _{TPM1CHx pins can be repositioned using TPM1PS in SOPT2, default reset locations are on PTA0 and}
PTB5.
4 _{This port pin is part of the ganged output feature. When pin is enabled for ganged output, it will have priority}
over all digital modules. The output data, drive strength and slew-rate control of this port pin will follow the
configuration for the PTC0 pin, even in 16-pin packages where PTC0 doesn’t bond out. Ganged output not
available in 8-pin packages.
5 _{If ACMP and ADC are both enabled, both will have access to the pin.}
MC9S08SG8 MCU Series Data Sheet, Rev. 0
Freescale Semiconductor
PRELIMINARY
29