S9S12G48F1CLC Datasheet, PDF (741/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Module (TIM16B6CV3)
Table 22-11. TSCR2 Field Descriptions
Field
7
TOI
2
PR[2:0]
Description
Timer Overflow Interrupt Enable
0 Interrupt inhibited.
1 Hardware interrupt requested when TOF flag set.
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
Bus Clock as shown in Table 22-12.
Table 22-12. Timer Clock Selection
PR2
PR1
PR0
Timer Clock
0
0
0
Bus Clock / 1
0
0
1
Bus Clock / 2
0
1
0
Bus Clock / 4
0
1
1
Bus Clock / 8
1
0
0
Bus Clock / 16
1
0
1
Bus Clock / 32
1
1
0
Bus Clock / 64
1
1
1
Bus Clock / 128
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
22.3.2.10 Main Timer Interrupt Flag 1 (TFLG1)
Module Base + 0x000E
7
6
5
4
3
2
1
0
R
RESERVED RESERVED
C5F
C4F
C3F
C2F
C1F
C0F
W
Reset
0
0
0
0
0
0
0
0
Figure 22-16. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
743