S9S12G48F1CLC Datasheet, PDF (366/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU)
Figure 10-2 shows a block diagram of the XOSCLCP.
Peak
Detector
OSCCLK_LCP
Gain Control
Clock
Monitor
monitor fail
VDD = 1.8 V
VSS
Rf
EXTAL
Quartz Crystals
or
Ceramic Resonators
XTAL
C1
C2
VSS
VSS
Figure 10-2. XOSCLCP Block Diagram
MC9S12G Family Reference Manual, Rev.1.23
368
Freescale Semiconductor