S9S12G48F1CLC Datasheet, PDF (400/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU)
Table 10-24. CPMUOSC Field Descriptions
Field
7
OSCE
Description
Oscillator Enable Bit — This bit enables the external oscillator (XOSCLCP). The UPOSC status bit in the
CPMUFLG register indicates when the oscillation is stable and OSCCLK can be selected as Bus Clock or source
of the COP or RTI. A loss of oscillation will lead to a clock monitor reset.
0 External oscillator is disabled.
REFCLK for PLL is IRCCLK.
1 External oscillator is enabled.Clock monitor is enabled.External oscillator is qualified by PLLCLK
REFCLK for PLL is the external oscillator clock divided by REFDIV.
6
Reserved
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop
Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time
of the external oscillator t_UPOSC before entering Pseudo Stop Mode.
Do not alter this bit from its reset value. It is for Manufacturer use only and can change the PLL behavior.
5
Oscillator Pins EXTAL and XTAL Enable Bit
OSCPINS_EN If OSCE=1 this read-only bit is set. It can only be cleared with the next reset.
Enabling the external oscillator reserves the EXTAL and XTAL pins exclusively for oscillator application.
0 EXTAL and XTAL pins are not reserved for oscillator.
1 EXTAL and XTAL pins exclusively reserved for oscillator.
4-0
Do not alter these bits from their reset value. It is for Manufacturer use only and can change the PLL behavior.
Reserved
MC9S12G Family Reference Manual, Rev.1.23
402
Freescale Semiconductor