S9S12G48F1CLC Datasheet, PDF (236/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12GPIMV1)
1 _{Read: Anytime}
Write: Anytime
Field
7-0
PIEJ
Table 2-73. PIEJ Register Field Descriptions
Description
Port J interrupt enable—
This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
2.4.3.48 Port J Interrupt Flag Register (PIFJ)
Address 0x026F (G1, G2)
7
R
PIFJ7
W
Reset
0
Address 0x026F (G3)
6
PIFJ6
0
5
PIFJ5
0
4
PIFJ4
0
3
PIFJ3
0
2
PIFJ2
0
7
6
5
4
3
2
R
0
0
0
0
PIFJ3
PIFJ2
W
Reset
0
0
0
0
0
0
Figure 2-48. Port J Interrupt Flag Register (PIFJ)
1 _{Read: Anytime}
Write: Anytime, write 1 to clear
Access: User read/write¹
1
0
PIFJ1
PIFJ0
0
0
Access: User read/write¹
1
0
PIFJ1
PIFJ0
0
0
Field
7-0
PIFJ
Table 2-74. PIFJ Register Field Descriptions
Description
Port J interrupt flag—
This flag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, “Pin Interrupts and
Wakeup”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will
occur if the associated interrupt enable bit is set.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred
0 No active edge occurred
MC9S12G Family Reference Manual, Rev.1.23
238
Freescale Semiconductor