S9S12G48F1CLC Datasheet, PDF (341/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

S12S Debug Module (S12SDBGV2)
8.4.5.3.1 Information Bit Organization
The format of the bits is dependent upon the active trace mode as described below.
Field2 Bits in Detail Mode
Bit 3
Bit 2
Bit 1
Bit 0
CSZ
CRW ADDR[17] ADDR[16]
Figure 8-25. Field2 Bits in Detail Mode
In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU.
Table 8-38. Field Descriptions
Bit
Description
3
CSZ
Access Type Indicator— This bit indicates if the access was a byte or word size when tracing in Detail Mode
0 Word Access
1 Byte Access
2
CRW
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access when tracing in Detail Mode.
0 Write Access
1 Read Access
1
Address Bus bit 17— Corresponds to system address bus bit 17.
ADDR[17]
0
Address Bus bit 16— Corresponds to system address bus bit 16.
ADDR[16]
Field2 Bits in Normal and Loop1 Modes
Bit 3
Bit 2
Bit 1
Bit 0
CSD
CVA
PC17
PC16
Figure 8-26. Information Bits PCH
Bit
3
CSD
2
CVA
1
PC17
Table 8-39. PCH Field Descriptions
Description
Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored
address is a source or destination address. This bit has no meaning in Compressed Pure PC mode.
0 Source Address
1 Destination Address
Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector
address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set.
This bit has no meaning in Compressed Pure PC mode.
0 Non-Vector Destination Address
1 Vector Destination Address
Program Counter bit 17— In Normal and Loop1 mode this bit corresponds to program counter bit 17.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
343