S9S12G48F1CLC Datasheet, PDF (228/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12GPIMV1)
2.4.3.36 Port P Data Direction Register (DDRP)
Address 0x025A (G1, G2)
7
R
DDRP7
W
Reset
0
Address 0x025A (G3)
6
DDRP6
0
5
DDRP5
0
4
DDRP4
0
3
DDRP3
0
2
DDRP2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
DDRP5
DDRP4
DDRP3
DDRP2
0
0
0
0
0
Figure 2-37. Port P Data Direction Register (DDRP)
Access: User read/write¹
1
0
DDRP1
DDRP0
0
0
Access: User read/write¹
1
0
DDRP1
DDRP0
0
0
Table 2-63. DDRP Register Field Descriptions
Field
7-0
DDRP
Description
Port P data direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
2.4.3.37 Port P Pull Device Enable Register (PERP)
Address 0x025C (G1, G2)
7
R
PERP7
W
Reset
0
Address 0x025C (G3)
6
PERP6
0
5
PERP5
0
4
PERP4
0
3
PERP3
0
2
PERP2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
PERP5
PERP4
PERP3
PERP2
0
0
0
0
0
Figure 2-38. Port P Pull Device Enable Register (PERP)
Access: User read/write¹
1
0
PERP1
PERP0
0
0
Access: User read/write¹
1
0
PERP1
PERP0
0
0
MC9S12G Family Reference Manual, Rev.1.23
230
Freescale Semiconductor