S9S12G48F1CLC Datasheet, PDF (401/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.20 S12CPMU Protection Register (CPMUPROT)
This register protects the following clock configuration registers from accidental overwrite:
CPMUSYNR, CPMUREFDIV, CPMUCLKS, CPMUPLL, CPMUIRCTRIMH/L and CPMUOSC
0x02FB
7
R
0
W
Reset
0
Read: Anytime
Write: Anytime
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-28. S12CPMU Protection Register (CPMUPROT)
0
PROT
0
Field
0
PROT
Description
Clock Configuration Registers Protection Bit — This bit protects the clock configuration registers from
accidental overwrite (see list of affected registers above):
Writing 0x26 to the CPMUPROT register clears the PROT bit, other write accesses set the PROT bit.
0 Protection of clock configuration registers is disabled.
1 Protection of clock configuration registers is enabled. (see list of protected registers above).
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
403