S9S12G48F1CLC Datasheet, PDF (609/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Freescale’s Scalable Controller Area Network (S12MSCANV3)
Figure 18-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued)
Register
Name
Bit 7
6
5
4
3
2
1
Bit0
= Unused, always read ‘x’
Read:
• For transmit buffers, anytime when TXEx flag is set (see Section 18.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
• For receive buffers, only when RXF flag is set (see Section 18.3.2.5, “MSCAN Receiver Flag
Register (CANRFLG)”).
Write:
• For transmit buffers, anytime when TXEx flag is set (see Section 18.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
• Unimplemented for receive buffers.
Reset: Undefined because of RAM-based implementation
Figure 18-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
IDR0
0x00X0
R
W
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
IDR1
R
0x00X1 _W
ID2
ID1
ID0
RTR
IDE (=0)
IDR2
R
0x00X2 _W
IDR3
R
0x00X3 _W
= Unused, always read ‘x’
18.3.3.1 Identifier Registers (IDR0–IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits: ID[28:0], SRR, IDE,
and RTR. The identifier registers for a standard format identifier consist of a total of 13 bits: ID[10:0],
RTR, and IDE.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
611