S9S12G48F1CLC Datasheet, PDF (183/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12GPIMV1)
PAD3
PAD2-PAD0
Table 2-17. Port AD Pins AD7-0 (continued)
• 20 TSSOP: The ACMPO signal of the analog comparator is mapped to this pin when used with the
ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to
output.
• The ADC analog input channel signal AN3 and the related digital trigger input are mapped to this pin.
The ADC function has no effect on the output state. Refer to NOTE/2-180 for input buffer control.
• Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
20 TSSOP: ACMPO > GPO
Others: GPO
• The ADC analog input channel signals AN2-0 and their related digital trigger inputs are mapped to this
pin. The ADC function has no effect on the output state. Refer to NOTE/2-180 for input buffer control.
• Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
GPO
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
185