S9S12G48F1CLC Datasheet, PDF (615/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Freescale’s Scalable Controller Area Network (S12MSCANV3)
Module Base + 0x00XD
Access: User read/write¹
7
R
PRIO7
W
6
PRIO6
5
PRIO5
4
PRIO4
3
PRIO3
2
PRIO2
1
PRIO1
0
PRIO0
Reset:
0
0
0
0
0
0
0
0
Figure 18-36. Transmit Buffer Priority Register (TBPR)
1 _{Read: Anytime when TXEx flag is set (see Section 18.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the}
corresponding transmit buffer is selected in CANTBSEL (see Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register
(CANTBSEL)”)
Write: Anytime when TXEx flag is set (see Section 18.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the
corresponding transmit buffer is selected in CANTBSEL (see Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register
(CANTBSEL)”)
18.3.3.5 Time Stamp Register (TSRH–TSRL)
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active
transmit or receive buffer right after the EOF of a valid message on the CAN bus (see Section 18.3.2.1,
“MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only read the time
stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
Module Base + 0x00XE
Access: User read/write¹
7
R TSR15
6
TSR14
5
TSR13
4
TSR12
3
TSR11
2
TSR10
1
TSR9
0
TSR8
W
Reset:
x
x
x
x
x
x
x
x
Figure 18-37. Time Stamp Register — High Byte (TSRH)
1 _{Read: Anytime when TXEx flag is set (see Section 18.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the}
corresponding transmit buffer is selected in CANTBSEL (see Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register
(CANTBSEL)”)
Write: Unimplemented
Module Base + 0x00XF
R
W
Reset:
7
TSR7
x
6
TSR6
5
TSR5
4
TSR4
3
TSR3
2
TSR2
Access: User read/write¹
1
TSR1
0
TSR0
x
x
x
x
x
x
x
Figure 18-38. Time Stamp Register — Low Byte (TSRL)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
617