S9S12G48F1CLC Datasheet, PDF (207/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12GPIMV1)
2.4.3.7 Port C Data Direction Register (DDRC)
Address 0x0006 (G1)
7
R
DDRC7
W
6
DDRC6
Reset
0
0
Address 0x0006 (G2, G3)
5
DDRC5
0
4
DDRA4
0
3
DDRC3
0
2
DDRC2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
Figure 2-8. Port C Data Direction Register (DDRC)
Access: User read/write¹
1
0
DDRC1
DDRC0
0
0
Access: User read only
1
0
0
0
0
0
Table 2-28. DDRC Register Field Descriptions
Field
7-0
DDRC
Description
Port C Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
2.4.3.8 Port D Data Direction Register (DDRD)
Address 0x0007 (G1)
7
R
DDRD7
W
6
DDRD6
Reset
0
0
Address 0x0007 (G2, G3)
5
DDRD5
0
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
Figure 2-9. Port D Data Direction Register (DDRD)
Access: User read/write¹
1
0
DDRD1
DDRD0
0
0
Access: User read only
1
0
0
0
0
0
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
209