S9S12G48F1CLC Datasheet, PDF (367/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.2 Signal Description
This section lists and describes the signals that connect off chip.
10.2.1 RESET
Pin RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered.
10.2.2 EXTAL and XTAL
These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is
the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. If
XOSCLCP is enabled, the MCU internal OSCCLK_LCP is derived from the EXTAL input frequency. If
OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 kΩ and the XTAL
pin is pulled down by an internal resistor of approximately 700 kΩ.
NOTE
Freescale recommends an evaluation of the application board and chosen
resonator or crystal by the resonator or crystal supplier.
The loop controlled circuit (XOSCLCP) is not suited for overtone
resonators and crystals.
10.2.3 VDDR — Regulator Power Input Pin
Pin VDDR is the power input of IVREG. All currents sourced into the regulator loads flow through this
pin.
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSS can smooth
ripple on VDDR.
10.2.4 VSS — Ground Pin
VSS must be grounded.
10.2.5 VDDA, VSSA — Regulator Reference Supply Pins
Pins VDDA and VSSA are used to supply the analog parts of the regulator.
Internal precision reference circuits are supplied from these signals.
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can improve
the quality of this supply.
10.2.6 VDDX, VSSX— Pad Supply Pins
This supply domain is monitored by the Low Voltage Reset circuit.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
369