S9S12G48F1CLC Datasheet, PDF (412/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU)
Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to
the CPMUARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out
period. A premature write will immediately reset the part.
10.5.3 Power-On Reset (POR)
The on-chip POR circuitry detects when the internal supply VDD drops below an appropriate voltage
level. The POR is deasserted, if the internal supply VDD exceeds an appropriate voltage level (voltage
levels are not specified in this document because this internal supply is not visible on device pins).
10.5.4 Low-Voltage Reset (LVR)
The on-chip LVR circuitry detects when one of the supply voltages VDD, VDDF or VDDX drops below
an appropriate voltage level. If LVR is deasserted the MCU is fully operational at the specified maximum
speed. The LVR assert and deassert levels for the supply voltage VDDX are V_LVRXA and V_LVRXD and are
specified in the device Reference Manual.
10.6 Interrupts
The interrupt/reset vectors requested by the S12CPMU are listed in Table 10-29. Refer to MCU
specification for related vector addresses and priorities.
Table 10-29. S12CPMU Interrupt Vectors
Interrupt Source
CCR
Mask
Local Enable
RTI time-out interrupt
I bit
PLL lock interrupt
I bit
Oscillator status
interrupt
I bit
Low voltage interrupt
I bit
Autonomous
Periodical Interrupt
I bit
CPMUINT (RTIE)
CPMUINT (LOCKIE)
CPMUINT (OSCIE)
CPMULVCTL (LVIE)
CPMUAPICTL (APIE)
10.6.1 Description of Interrupt Operation
10.6.1.1 Real Time Interrupt (RTI)
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), RTIOSCSEL=1 and PRE=1 the RTI continues to
run, else the RTI counter halts in Stop Mode.
MC9S12G Family Reference Manual, Rev.1.23
414
Freescale Semiconductor