S9S12G48F1CLC Datasheet, PDF (233/1292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12GPIMV1)
2.4.3.43 Port J Input Register (PTIJ)
Address 0x0269 (G1, G2)
7
R PTIJ7
W
Reset
0
Address 0x0269 (G3)
6
PTIJ6
0
7
6
R
0
0
W
Reset
0
0
1 _{Read: Anytime}
Write:Never
5
PTIJ5
0
4
PTIJ4
0
3
PTIJ3
0
2
PTIJ2
0
5
4
3
2
0
0
PTIJ3
PTIJ2
0
0
0
0
Figure 2-43. Port J Input Register (PTIJ)
Access: User read only¹
1
PTIJ1
0
PTIJ0
0
0
Access: User read only¹
1
PTIJ1
0
PTIJ0
0
0
Field
7-0
PTIJ
Table 2-69. PTIJ Register Field Descriptions
Description
Port J input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.4.3.44 Port J Data Direction Register (DDRJ)
Address 0x026A (G1, G2)
7
R
DDRJ7
W
Reset
0
Address 0x026A (G3)
6
DDRJ6
0
5
DDRJ5
0
4
DDRJ4
0
3
DDRJ3
0
2
DDRJ2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
DDRJ3
DDRJ2
0
0
0
0
0
Figure 2-44. Port J Data Direction Register (DDRJ)
Access: User read/write¹
1
0
DDRJ1
DDRJ0
0
0
Access: User read/write¹
1
0
DDRJ1
DDRJ0
0
0
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
235