MC9328MX1 Datasheet, PDF (74/96 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
Table 33. PWM Output Timing Parameter Table (Continued)
Ref
No.
Parameter
3a Clock fall time¹
3b Clock rise time¹
4a Output delay time¹
4b Output setup time¹
1. C_L of PWMO = 30 pF
1.8V +/- 0.10V
Minimum
–
–
5.7
5.7
Maximum
5
6.67
–
–
3.0V +/- 0.30V
Unit
Minimum
Maximum
–
5/10
ns
–
5/10
ns
5
–
ns
5
–
ns
3.18 SDRAM Memory Controller
A write to an address within the memory region initiates the program sequence. The first command issued to the
SyncFlash is Load Command Register. A [7:0] determine which operation the command performs. For this write
setup operation, an address of 0x40 is hardware generated. The bank and other address lines are driven with the
address to be programmed. The next command is Active which registers the row address and confirms the bank
address. The third command supplies the column address, re-confirms the bank address, and supplies the data to be
written. SyncFlash does not support burst writes, therefore a Burst Terminate command is not required.
A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash is the
Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register operation. The
bank and other address lines are driven to the selected address. The second command is Active which sets up the
status register read. The bank and row addresses are driven during this command. The third command of the triplet
is Read. Bank and column addresses are driven on the address bus during this command. Data is returned from
memory on the low order 8 data bits following the CAS latency.
MC9328MX1 Advance Information, Rev. 4
74
Freescale Semiconductor