MC9328MX1 Datasheet, PDF (64/96 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
3.15 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal MMC/SD
module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of
FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and
the application (user programming).
Bus Clock
CMD_DAT Input
3a
4a
5a
Valid Data
CMD_DAT Output
12
3b
4b
7
Valid Data
6a
5b
Valid Data
Valid Data
6b
Figure 47. Chip-Select Read Cycle Timing Diagram
Table 29. SDHC Bus Timing Parameter Table
Ref
No.
Parameter
1.8V +/- 0.10V
Min
Max
3.0V +/- 0.30V
Min Max
1 CLK frequency at Data transfer Mode (PP)¹â€”10/30 cards
0
2 CLK frequency at Identification Mode²
0
3a Clock high time¹â€”10/30 cards
6/33
3b Clock low time¹â€”10/30 cards
15/75
4a Clock fall time¹â€”10/30 cards
–
4b Clock rise time¹â€”10/30 cards
–
5a Input hold time³â€”10/30 cards
5b Input setup time³â€”10/30 cards
6a Output hold time³â€”10/30 cards
6b Output setup time³â€”10/30 cards
7 Output delay time³
1. C_L ≤ 100 pF / 250 pF (10/30 cards)
2. C_L ≤ 250 pF (21 cards)
3. C_L ≤ 25 pF (1 card)
5.7/5.7
5.7/5.7
5.7/5.7
5.7/5.7
0
25/5
400
–
–
10/50 (5.00)³
14/67 (6.67)³
–
–
–
–
16
0
0
10/50
10/50
–
–
5/5
5/5
5/5
5/5
0
25/5
400
–
–
10/50
10/50
–
–
–
–
14
Unit
MHz
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MC9328MX1 Advance Information, Rev. 4
64
Freescale Semiconductor