MC9328MX1 Datasheet, PDF (65/96 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
3.15.1 Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card response
to the host command starts after exactly N_ID clock cycles. For the card address assignment, SET_RCA is also
processed in the open-drain mode. The minimum delay between the host command and card response is NCR
clock cycles as illustrated in Figure 48. The symbols for Figure 48 through Figure 52 are defined in Table 30.
Table 30. State Signal Parameters for Figure 48 through Figure 52
Card Active
Host Active
Symbol
Definition
Symbol
Definition
Z
High impedance state
S
Start bit (0)
D
Data bits
T
Transmitter bit
(Host = 1, Card = 0)
*
Repetition
P
One-cycle pull-up (1)
CRC Cyclic redundancy check bits (7 bits)
E
End bit (1)
Host Command
CMD S T Content CRC E Z
N_ID cycles
CID/OCR
******
Z S T Content Z Z Z
Identification Timing
Host Command
CMD _{S T} Content CRC _{E Z}
N_CR cycles
CID/OCR
******
Z S T Content Z Z Z
SET_RCA Timing
Figure 48. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in Figure 49 on
page 66, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a period of
two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding card.
The other two diagrams show the separating periods N_RC and N_CC.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
65