MC9328MX1 Datasheet, PDF (53/96 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

LSCLK
Specifications
LD[15:0]
1
Figure 33. SCLK to LD Timing Diagram
Table 18. LCDC SCLK Timing
Num
Characteristic
3.0 +/- 0.3V
Unit
Minimum Maximum
1 SCLK to LD valid
–
3
ns
3.9.4 Non-TFT Panel Timing
T1
T1
VSYN
T2
HSYN
SCLK
T3
XMAX
T4
T2
Ts
LD[15:0]
Figure 34. Non-TFT Panel Timing
Table 19. Non TFT Panel Timing Diagram
Symbol
Parameter
Allowed Register Minimum
Value
Actual Value
Unit
T1
HSYN to VSYN delay
T2
HSYN pulse width
T3
VSYN to SCLK
T4
SCLK to HSYN
0
HWAIT2+2
Tpix
0
HWIDTH+1
Tpix
–
0<= T3<=Ts
–
0
HWAIT1+1
Tpix
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
53