MC9328MX1 Datasheet, PDF (28/96 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
3.9.2.4 DTACK Write Cycle DMA Enabled
Address
(1)
CS5
(2)
EB
(3)
programmable
min 0ns
programmable
min 0ns
RW
(7)
(5)
(10)
(11)
(4)
OE(logic ^high)
(6)
DTACK
(9)
(12)
Databus
(output from MX1)
(8)
Figure 9. DTACK Write Cycle DMA Enabled
Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
1
CS5 assertion time
2
EB assertion time
3
CS5 pulse width
4
RW negated before CS5 is negated
5
Address inactive before CS negated
6
DTACK asserted after CS5 asserted
See note 2
See note 2
3T
1.5T+0.58
–
–
–
ns
–
ns
–
ns
1.5T+1.58
ns
0.93
ns
1019T
ns
MC9328MX1 Advance Information, Rev. 4
28
Freescale Semiconductor