MC9328MX1 Datasheet, PDF (73/96 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
Table 32. MSHC Signal Timing Parameter Table (Continued)
Ref No.
Parameter
Minimum Maximum Unit
11
MS_BS delay time¹
12
MS_SDIO output delay time^1,2
13
MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)³
14
MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)³
15
MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)⁴
16
MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)⁴
–
3
ns
–
3
ns
18
–
ns
0
–
ns
23
–
ns
0
–
ns
1. Loading capacitor condition is less than or equal to 30pF.
2. An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the MS_SDIO pin,
because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick SDIO pin when the pin
direction changes.
3. If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge.
4. If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.
3.17 Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal
is passed through a divider and a prescaler before being input to the counter. The output is available at the pulse-
width modulator output (PWMO) external pin.
System Clock
PWM Output
2a
2b
4a
1
3b
3a
4b
Figure 56. PWM Output Timing Diagram
Table 33. PWM Output Timing Parameter Table
Ref
No.
Parameter
1
System CLK frequency¹
2a Clock high time¹
2b Clock low time¹
1.8V +/- 0.10V
Minimum
0
3.3
7.5
Maximum
87
–
–
3.0V +/- 0.30V
Minimum
0
5/10
5/10
Maximum
100
–
–
Unit
MHz
ns
ns
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
73