MC9328MX1 Datasheet, PDF (24/96 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
3.9.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a
data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the
external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group supports DTACK signal
function when the external DTACK signal is used for data acknowledgement.
3.9.2 DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of
measure for this figure are found in the associated tables.
3.9.2.1 DTACK READ Cycle without DMA
Address
CS5
(1)
EB
(2)
programmable
min 0ns
(3)
(8)
(9)
OE
(5)
(4)
DTACK
Databus
(input to MX1)
(6)
(10)
(7)
Figure 6. DTACK READ Cycle without DMA
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
1
OE and EB assertion time
See note 2
–
ns
2
CS5 pulse width
3
OE negated to address inactive
4
DTACK asserted after CS5 asserted
3T
46.44
–
–
ns
–
ns
1019T
ns
MC9328MX1 Advance Information, Rev. 4
24
Freescale Semiconductor