MC9328MX1 Datasheet, PDF (27/96 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

3.9.2.3 DTACK Write Cycle without DMA
Address
(1)
CS5
(2)
EB
RW
(3)
programmable
min 0ns
programmable
min 0ns
(7)
Specifications
(5)
(10)
(4)
OE(logic ^high)
(6)
DTACK
(9)
Databus
(output from MX1)
(11)
(8)
Figure 8. DTACK Write Cycle without DMA
Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
1
CS5 assertion time
2
EB assertion time
3
CS5 pulse width
4
RW negated before CS5 is negated
5
RW negated to Address inactive
6
DTACK asserted after CS5 asserted
7
DTACK asserted to RW negated
8
Data hold timing after RW negated
9
Data ready after CS5 is asserted
10
EB negated before CS5 is negated
11
DTACK pulse width
See note 2.
See note 2
3T
1.5T+0.58
57.31
–
2T+1.8
1.5T-0.59
–
0.5T+0.74
1T
–
ns
–
ns
–
ns
1.5T+1.58
ns
–
ns
1019T
ns
3T+5.26
ns
–
ns
T
ns
0.5T+2.17
ns
3T
ns
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
27