MC9328MX1 Datasheet, PDF (25/96 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
5
DTACK asserted to OE negated
3T+2.2
4T+6.86
ns
6
Data hold timing after OE negated
0
–
ns
7
Data ready after DTACK asserted
0
T
ns
8
OE negated to CS negated
0.5T+0.24
0.5T+0.67
ns
9
OE negated after EB negated
0.5
1.5
ns
10
DTACK pulse width
1T
3T
ns
Note:
0. DTACK assert means DTACK become low level.
1. T is the system clock period. (For 96MHz system clock)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur
only when EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
3.9.2.2 DTACK Read Cycle DMA Enabled
Address
CS5
(1)
EB
OE
(2)
programmable
min 0ns
(6)
(4)
(9)
(10)
(3)
RW(logic ^high)
DTACK
Databus
(input to MX1)
(5)
(7)
(11)
(8)
Figure 7. DTACK Read Cycle DMA Enabled
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
25