MC9328MX1 Datasheet, PDF (66/96 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
Host Command
N_CR cycles
CMD S T Content CRC E Z Z P ****** P S T
Response
Content CRC E Z Z Z
Command response timing (data transfer mode)
CMD S T
Response
N_RC cycles
Host Command
Content CRC E Z
******
Z S T Content CRC E Z Z Z
Timing response end to next CMD start (data transfer mode)
Host Command
CMD S T Content CRC E Z
N_CC cycles
Host Command
****** Z S T Content CRC E Z Z Z
Timing of command sequences (all modes)
Figure 49. Timing Diagrams at Data Transfer Mode
Figure 50 on page 67 shows basic read operation timing. In a read operation, the sequence starts with a single block
read command (which specifies the start address in the argument field). The response is sent on the SD_CMD lines
as usual. Data transmission from the card starts after the access time delay N_AC, beginning from the last bit of the
read command. If the system is in multiple block read mode, the card sends a continuous flow of data blocks with
distance N_AC until the card sees a stop transmission command. The data stops two clock cycles after the end bit of
the stop command.
MC9328MX1 Advance Information, Rev. 4
66
Freescale Semiconductor