MC9328MX1 Datasheet, PDF (19/96 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
3.7 DPLL Timing Specifications
Parameters of the DPLL are given in Table 11. In this table, T_ref is a reference clock period after the pre-divider
and T_dck is the output double clock period.
Table 11. DPLL Specifications
Parameter
Test Conditions
Minimum Typical Maximum Unit
Reference clock freq range Vcc = 1.8V
5
–
100
MHz
Pre-divider output clock
freq range
Vcc = 1.8V
5
–
30
MHz
Double clock freq range
Vcc = 1.8V
80
–
220
MHz
Pre-divider factor (PD)
–
1
–
16
–
Total multiplication factor
(MF)
Includes both integer
and fractional parts
5
–
15
–
MF
–
integer part
5
–
15
–
MF
numerator
Should be less than the
denominator
0
–
1022
–
MF
–
denominator
1
–
1023
–
Pre-multiplier lock-in time –
–
–
312.5
µsec
Freq lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-must lock-in time)
250
280
300
T_ref
(56 µs)
Freq lock-in time after
partial reset
FOL mode for non-integer MF (does not
include pre-multi lock-in time)
220
250
270
T_ref
(~50 µs)
Phase lock-in time after
FPL mode and integer MF (does not include
300
350
400
T_ref
full reset
pre-multi lock-in time)
(70 µs)
Phase lock-in time after
FPL mode and integer MF (does not include
270
320
370
T_ref
partial reset
pre-multi lock-in time)
(64 µs)
Freq jitter (p-p)
–
–
0.005
0.01
2•T_dck
(0.01%)
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
–
1.0
1.5
ns
(10%)
Power supply voltage
–
1.7
–
2.5
V
Power dissipation
FOL mode, integer MF,
f_dck = 200 MHz, Vcc = 1.8V
–
–
4
mW
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
19