MC9328MX1 Datasheet, PDF (29/96 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

Specifications
Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz (Continued)
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
7
DTACK asserted to RW negated
2T+1.8
3T+5.26
ns
8
Data hold timing after RW negated
1.5T-0.59
–
ns
9
Data ready after CS5 is asserted
–
T
ns
10
CS deactive to next CS active
T
–
ns
11
EB negate to CS negate
0.5T+0.74
0.5T+2.17
ns
12
DTACK pulse width
1T
3T
ns
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4.The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
29