MC9328MX1 Datasheet, PDF (61/96 Pages) Freescale Semiconductor, Inc – i.MX Integrated Portable System Processor

SS (output)
Specifications
SCLK, MOSI, MISO
Figure 42. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger
SS (input)
SCLK, MOSI, MISO
Figure 43. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
SS (input)
6
7
SCLK, MOSI, MISO
Figure 44. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge
Table 26. Timing Parameter Table for Figure 40 through Figure 44
Ref
No.
Parameter
Minimum
Maximum Unit
1 SPI_RDY to SS output low
2T ¹
–
ns
2 SS output low to first SCLK edge
3·Tsclk ²
–
ns
3 Last SCLK edge to SS output high
2·Tsclk
–
ns
4 SS output high to SPI_RDY low
0
–
ns
5 SS output pulse width
Tsclk + WAIT ³
–
ns
6 SS input low to first SCLK edge
T
–
ns
7 SS input pulse width
T
–
ns
1. T = CSPI system clock period (PERCLK2).
2. Tsclk = Period of SCLK.
3. WAIT = Number of bit clocks (SCLK) or 32.768 KHz clocks per Sample
Period Control Register.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
61