S9S12GN32F0MLC Datasheet, PDF (707/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Serial Peripheral Interface (S12SPIV5)
Register
Name
Bit 7
6
5
4
3
2
0x0005
R
R7
R6
R5
R4
R3
R2
SPIDRL _W
T7
T6
T5
T4
T3
T2
0x0006
R
Reserved _W
0x0007
R
Reserved _W
= Unimplemented or Reserved
Figure 21-2. SPI Register Summary
1
Bit 0
R1
R0
T1
T0
21.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
21.3.2.1 SPI Control Register 1 (SPICR1)
Module Base +0x0000
R
W
Reset
7
SPIE
0
Read: Anytime
Write: Anytime
6
SPE
5
SPTIE
4
MSTR
3
CPOL
2
CPHA
0
0
0
0
1
Figure 21-3. SPI Control Register 1 (SPICR1)
Table 21-1. SPICR1 Field Descriptions
1
SSOE
0
0
LSBFE
0
Field
7
SPIE
6
SPE
5
SPTIE
Description
SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.
0 SPI interrupts disabled.
1 SPI interrupts enabled.
SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system
functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.
0 SPI disabled (lower power consumption).
1 SPI enabled, port pins are dedicated to SPI functions.
SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set.
0 SPTEF interrupt disabled.
1 SPTEF interrupt enabled.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
709