S9S12GN32F0MLC Datasheet, PDF(374/1292 Page) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

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S9S12GN32F0MLC Datasheet, PDF (374/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

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S12 Clock, Reset and Power Management Unit (S12CPMU)

Table 10-3. CPMUFLG Field Descriptions

Field

7

RTIF

6

PORF

5

LVRF

4

LOCKIF

3

LOCK

2

ILAF

1

OSCIF

0

UPOSC

Description

Real Time Interrupt Flag â RTIF is set to 1 at the end of the RTI period. This ï¬ag can only be cleared by writing

a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.

0 RTI time-out has not yet occurred.

1 RTI time-out has occurred.

Power on Reset Flag â PORF is set to 1 when a power on reset occurs. This ï¬ag can only be cleared by writing

a 1. Writing a 0 has no effect.

0 Power on reset has not occurred.

1 Power on reset has occurred.

Low Voltage Reset Flag â LVRF is set to 1 when a low voltage reset occurs. This ï¬ag can only be cleared by

writing a 1. Writing a 0 has no effect.

0 Low voltage reset has not occurred.

1 Low voltage reset has occurred.

PLL Lock Interrupt Flag â LOCKIF is set to 1 when LOCK status bit changes. This ï¬ag can only be cleared by

writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.

0 No change in LOCK bit.

1 LOCK bit has changed.

Lock Status Bit â LOCK reï¬ects the current state of PLL lock condition. Writes have no effect. While PLL is

unlocked (LOCK=0) fPLL is fVCO / 4 to protect the system from high core clock frequencies during the PLL

stabilization time tlock.

0 VCOCLK is not within the desired tolerance of the target frequency.

fPLL = fVCO/4.

1 VCOCLK is within the desired tolerance of the target frequency.

fPLL = fVCO/(POSTDIV+1).

Illegal Address Reset Flag â ILAF is set to 1 when an illegal address reset occurs. Refer to MMC chapter for

details. This ï¬ag can only be cleared by writing a 1. Writing a 0 has no effect.

0 Illegal address reset has not occurred.

1 Illegal address reset has occurred.

Oscillator Interrupt Flag â OSCIF is set to 1 when UPOSC status bit changes. This ï¬ag can only be cleared

by writing a 1. Writing a 0 has no effect.If enabled (OSCIE=1), OSCIF causes an interrupt request.

0 No change in UPOSC bit.

1 UPOSC bit has changed.

Oscillator Status Bit â UPOSC reï¬ects the status of the oscillator. Writes have no effect. While UPOSC=0 the

OSCCLK going to the MSCAN module is off. Entering Full Stop Mode UPOSC is cleared.

0 The oscillator is off or oscillation is not qualiï¬ed by the PLL.

1 The oscillator is qualiï¬ed by the PLL.

MC9S12G Family Reference Manual, Rev.1.23

376

Freescale Semiconductor

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