S9S12GN32F0MLC Datasheet, PDF (205/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
2.4.3.4 Port B Data Direction Register (DDRB)
Address 0x0003 (G1)
7
R
DDRB7
W
6
DDRB6
Reset
0
0
Address 0x0003 (G2, G3)
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
Figure 2-5. Port B Data Direction Register (DDRB)
Access: User read/write¹
1
0
DDRB1
DDRB0
0
0
Access: User read only
1
0
0
0
0
0
Table 2-25. DDRB Register Field Descriptions
Field
7-0
DDRB
Description
Port B Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
2.4.3.5 Port C Data Register (PORTC)
Address 0x0004 (G1)
7
R
PC7
W
6
PC6
Reset
0
0
Address 0x0004 (G2, G3)
5
PC5
0
4
PC4
0
3
PC3
0
2
PC2
0
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
Figure 2-6. Port C Data Register (PORTC)
1 _{Read: Anytime. The data source is depending on the data direction value.}
Write: Anytime
Access: User read/write¹
1
0
PC1
PC0
0
0
Access: User read only
1
0
0
0
0
0
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
207