S9S12GN32F0MLC Datasheet, PDF (1209/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Electrical Characteristics
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
Table A-19. ADC Operating Characteristics
Supply voltage 3.13 V < V_DDA < 5.5 V, -40^oC < T_J < T_Jmax1
Num C
Rating
Symbol
Min
Typ
Max
Unit
1 D Reference potential
Low
High
V_RL
V_SSA
—
V_DDA/2
V
V_RH
V_DDA/2
—
V_DDA
V
2 D Voltage difference V_DDX to V_DDA
∆_VDDX
–2.35
0
0.1
V
3 D Voltage difference V_SSX to V_SSA
∆_VSSX
–0.1
0
0.1
V
4 C Differential reference voltage
V_RH-V_RL
3.13
5.0
5.5
V
5 C ADC Clock Frequency (derived from bus clock via the
0.25
prescaler bus)
f_ATDCLk
8.0
MHz
ADC Conversion Period²
8 D ^{12 bit resolution:}
10 bit resolution:
8 bit resolution:
N_CONV12
20
N_CONV10
19
N_CONV8
17
42
ADC
41
clock
39
Cycles
1 _{see Table A-4}
2 _{The minimum time assumes a sample time of 4 ADC clock cycles. The maximum time assumes a sample time of 24 ADC}
clock cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ADC clock cycles.
A.4.2 Factors Influencing Accuracy
Source resistance, source capacitance and current injection have an influence on the accuracy of the ADC.
A further factor is that port AD pins that are configured as output drivers switching.
A.4.2.1 Differential Reference Voltage
The accuracy is reduced if the differential reference voltage is less than 3.13V when using the ATD in the
3.3V range or if the differential reference voltage is less than 4.5V when using the ATD in the 5V range.
A.4.2.2 Port AD Output Drivers Switching
Port AD output drivers switching can adversely affect the ADC accuracy whilst converting the analog
voltage on other port AD pins because the output drivers are supplied from the VDDA/VSSA ADC supply
pins. Although internal design measures are implemented to minimize the affect of output driver noise, it
is recommended to configure port AD pins as outputs only for low frequency, low load outputs. The impact
on ADC accuracy is load dependent and not specified. The values specified are valid under condition that
no port AD output drivers switch during conversion.
A.4.2.3 Source Resistance
Due to the input pin leakage current as specified in conjunction with the source resistance there will be a
voltage drop from the signal source to the ADC input. The maximum source resistance R_S specifies results
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MC9S12G Family Reference Manual, Rev.1.23
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