S9S12GN32F0MLC Datasheet, PDF (327/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12S Debug Module (S12SDBGV2)
Table 8-23. Read or Write Comparison Logic Table
RWE Bit
0
0
1
1
1
1
RW Bit
x
x
0
0
1
1
RW Signal
0
1
0
1
0
1
Comment
RW not used in comparison
RW not used in comparison
Write data bus
No match
No match
Read data bus
8.3.2.8.2 Debug Comparator Address High Register (DBGXAH)
Address: 0x0029
7
R
0
W
Reset
0
6
5
4
3
2
1
0
0
0
0
0
Bit 17
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-16. Debug Comparator Address High Register (DBGXAH)
0
Bit 16
0
The DBGC1_COMRV bits determine which comparator address registers are visible in the 8-byte window
from 0x0028 to 0x002F as shown in Section Table 8-24., “Comparator Address Register Visibility
Table 8-24. Comparator Address Register Visibility
COMRV
00
01
10
11
Visible Comparator
DBGAAH, DBGAAM, DBGAAL
DBGBAH, DBGBAM, DBGBAL
DBGCAH, DBGCAM, DBGCAL
None
Read: Anytime. See Table 8-24 for visible register encoding.
Write: If DBG not armed. See Table 8-24 for visible register encoding.
Table 8-25. DBGXAH Field Descriptions
Field
Description
1–0
Bit[17:16]
Comparator Address High Compare Bits — The Comparator address high compare bits control whether the
selected comparator compares the address bus bits [17:16] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
329