S9S12GN32F0MLC Datasheet, PDF (1241/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Electrical Characteristics
A.15 SPI Timing
This section provides electrical parametrics and ratings for the SPI. In Table A-46 the measurement
conditions are listed.
Table A-46. Measurement Conditions
Conditions are 4.5 V < V_DD35 < 5.5 V junction temperature from –40°C to T_Jmax
Description
Value
Unit
Drive mode
Full drive mode
—
Load capacitance C_LOAD1, on all outputs
50
pF
Thresholds for delay measurement points
(35% / 65%) V_DDX
V
1 _{Timing specified for equal load on all SPI output pins. Avoid asymmetric load.}
A.15.1 Master Mode
In Figure A-7 the timing diagram for master mode with transmission format CPHA = 0 is depicted.
SS
(Output)
SCK
(CPOL = 0)
(Output)
SCK
(CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
2
1
12
4
4
12
5
6
MSB IN2
10
MSB OUT2
Bit MSB-1. . . 1
9
Bit MSB-1. . . 1
13
13
LSB IN
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB.
Figure A-7. SPI Master Timing (CPHA = 0)
3
11
Freescale Semiconductor
MC9S12G Family Reference Manual, Rev.1.23
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