S9S12GN32F0MLC Datasheet, PDF (208/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
Table 2-29. DDRD Register Field Descriptions
Field
7-0
DDRD
Description
Port D Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
2.4.3.9 Port E Data Register (PORTE)
Address 0x0008
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
Figure 2-10. Port E Data Register (PORTE)
1 _{Read: Anytime. The data source is depending on the data direction value.}
Write: Anytime
Access: User read/write¹
1
0
PE1
PE0
0
0
Field
1-0
PE
Table 2-30. PORTE Register Field Descriptions
Description
Port E general-purpose input/output data—Data Register
When not used with an alternative signal, this pin can be used as general-purpose I/O.
In general-purpose output mode the port data register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2.4.3.10 Port E Data Direction Register (DDRE)
Address 0x0009
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
Figure 2-11. Port E Data Direction Register (DDRE)
Access: User read/write¹
1
0
DDRE1
DDRE0
0
0
MC9S12G Family Reference Manual, Rev.1.23
210
Freescale Semiconductor