S9S12GN32F0MLC Datasheet, PDF (383/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.9 S12CPMU COP Control Register (CPMUCOP)
This register controls the COP (Computer Operating Properly) watchdog.
The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL0 and COPOSCSEL1 bit (see also Table 10-6).
In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL0=1 and COPOSCEL1=0 and PCE=1 the
COP continues to run, else the COP counter halts in Stop Mode with COPOSCSEL1 =0.
In Full Stop Mode and Pseudo Stop Mode with COPOSCSEL1=1 the COP continues to run.
0x003C
7
6
5
4
R
0
0
WCOP
RSBCK
W
WRTMASK
3
2
1
0
0
CR2
CR1
CR0
Reset
F
0
0
0
0
F
F
F
After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for
details.
= Unimplemented or Reserved
Figure 10-12. S12CPMU COP Control Register (CPMUCOP)
Read: Anytime
Write:
1. RSBCK: Anytime in Special Mode; write to “1” but not to “0” in Normal Mode
2. WCOP, CR2, CR1, CR0:
— Anytime in Special Mode, when WRTMASK is 0, otherwise it has no effect
— Write once in Normal Mode, when WRTMASK is 0, otherwise it has no effect.
– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
– Writing WCOP to “0” has no effect, but counts for the “write once” condition.
When a non-zero value is loaded from Flash to CR[2:0] the COP time-out period is started.
A change of the COPOSCSEL0 or COPSOCSEL1 bit (writing a different value) or loosing UPOSC status
while COPOSCSEL1 is clear and COPOSCSEL0 is set, re-starts the COP time-out period.
In Normal Mode the COP time-out period is restarted if either of these conditions is true:
1. Writing a non-zero value to CR[2:0] (anytime in Special Mode, once in Normal Mode) with
WRTMASK = 0.
2. Writing WCOP bit (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0.
3. Changing RSBCK bit from “0” to “1”.
In Special Mode, any write access to CPMUCOP register restarts the COP time-out period.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
385